Division of binary polynomials has application in transmits data via ISDN, in particular, for generating header error codes from input code vectors. Specifically, section 4.3 ("Header error control") of ITU-T Recommendation 1.432 discusses that an input code vector consisting of ones and zeros can be represented by a polynomial. For example, the code vector 1000000100001 can be represented by the polynomial EQU P(x)=x.sup.12 +x.sup.5 +1.
According to the ITU-T Recommendation, the header control (HEC) field "shall be the remainder of the division (modulo 2) by the generator polynomial EQU x.sup.8 +x.sup.2 +x+1
of the product x.sup.8 multiplied by the content of the header excluding the HEC field."
Conventionally, in order to determine the remainder of the above-mentioned modulo 2 division, a linear switching circuit is employed. Such linear switching circuits are well-known in the art and are described, for example, in Chapter 7 (pp. 170-178) of Error-Correcting Codes (Second Edition), published by the Massachusetts Institute of Technology in 1972, and authored by W. Wesley Peterson and E. J. Weldon. A disadvantage of using linear switching circuits for polynomial division is that these linear switching circuits require as many clock cycles to complete the division as the degree of the polynomial divisor.